Publications:
U.B.S. Chandrawat and D.K. Mishra, Relationship between settling time and pole– zero placements for three-stage CMOS opamp International Journal of Electronics, Taylor and Francis, vol. 98, pp.901-922,2011.
U.B.S. Chandrawat and D.K. Mishra, Design procedure for two-stage CMOS opamp with optimum balancing of speed, power and noise International Journal of Electronics, Taylor and Francis, vol. 96, no.11, pp.1145-1159, 2009.
U.B.S. Chandrawat and D.K. Mishra, “Fast settling opamp with low power consumption” International Journal of Electronics, Taylor and Francis, vol. 94, pp.683-698, 2007.
U.B.S. Chandrawat and D.K. Mishra, “A Design Technique based on pole- zero placements for Fast Settling, Low Power Operational Amplifier”, International Journal of Electronic Engineering Research ISSN 0975 – 6450 Volume 2, Number 3, pp. 281–294, 2010.
U.B.S. Chandrawat and D.K. Mishra, “An Analytical Model for the Slewing Behavior of Three-Stage CMOS Operational Amplifiers” , International Journal of Electronic Engineering Research ISSN 0975 - 6450 Volume 2 Number 3, pp. 269– 279, 2010.
U.B.S. Chandrawat and D.K. Mishra, “A Novel Design Technique for Fast Settling, Low Power Operational Amplifier ” in proceedings of International conference on Mems & Optoelectronics Technologies, SCET & IACQER, Narsapur (A.P.), pp. 264-272, 22nd -23rd January 2010.
U.B.S. Chandrawat and D.K. Mishra, “A Time-Domain model for the Slewing Behavior of Three- Stage CMOS Operational Amplifier” in proceedings of International conference on Mems & Optoelectronics Technologies, SCET & IACQER, Narsapur (A.P.), pp. 185-190, 22nd -23rd January 2010.
U.B.S. Chandrawat, “Fast settling operational amplifier with low power consumption” Proceedings of the Second Control Instrumentation System Conference (CISCON-2005) at Manipal Institute of Technology, pp. 309-313, Nov. 2005.
M. Sakare, U.B.S. Chandrawat, D.S. Ajnar “Study of operational amplifier design strategies for on chip measurement system”, National level conference NCETTIT -2007, SGSITS Indore on 18-20 Dec 07
M. Sakare, U.B.S. Chandrawat, D.S. Ajnar “ Design of Two-Stage CMOS Opamp with flexible Noise- Power Balancing scheme in 0.35 µm technology”, National level conference ETEET -2008, M.I.T. Ujjain, 23-24 February 08.
U.B.S. Chandrawat, National level conference “SANGOSHTHI -05” at MIT Mandsaur, paper presented on “Self Employment Based Technical Education”.
Anshu Gupta, D.K. Mishra, UBS Chandrawat, Prit Jain "A two stage and three stage CMOS OPAMP with fast settling, high DC gain and low power designed in 180nm technology", Computer Information Systems and Industrial Management Applications (CISIM), 2010 International Conference, pp. 448-453, Publisher-IEEE.
Ankush B., S. Daultabad, UBS Chandrawat, "Design of 3 bit MDAC for pipeline ADC", Vol.2 Issue10, October-2013, PP: SZ to 3199 IJERT (International Journal of Engineering Research and Technology) ISSN:2278-0181 peer reviewed.
Ankit Jain, UBS Chandrawat, " FPGA Design for Implementing data acquisition using
SDRAM" , PP:164-168, Vol.2, issue2, International Journal of Advancements in Electronics
and Electrical Engineering, ISSN: 2319-7498.
Vijay Sharma, UBS Chandrawat, " A 2.5 V, 10-bit 5 MS/s Pipeline ADC using Capacitor
opamp sharing Technique", Vol.1 issue4, PP:51-54, International Journal of Electronics &
Communication Engineering Research (IJECER), ISSN: 2321-9718.
Rajesh Nagar, UBS Chandrawat, "Design of a 3.0 MSPS, 2.4V, 0.25 m, 4-Bit Flash ADC
Based on TIQ Comparator ",Vol. 12, No.3 PP. 123-126, International Journal of Engineering
Trends and Technology (IJETT), ISSN: 2231-5381
. Rajesh Nagar, UBS Chandrawat, CMOS Inverter based comparator for the design of A 4-Bit
Flash ADC Vol. IV issue V June 2014, PP: 1-4, International Journal of Electrical,
Electronics & Communication Engineering , ISSN: 2319-2232
Vijay Sharma, UBS Chandrawat, "1.5 bit per stage pipeline ADC using capacitor sharing
technique". Vol. III Issue X oct.2013, PP: 471-474, International Journal of Electrical,
Electronics & Communication Engineering, ISSN: 2319-2232
Swati Singh, UBS Chandrawat, "Built –in –self test for embedded memories by finite state
machine" Vol.2, issue2, September 2013, International Journal of Digital Application &
contemporary research, ISSN: 2319-4863, Impact factor: 1.939
Shyam Singh Dangi, U.B.S. Chandrawat "A novel architecture of 8 bit pipeline ADC using
EDA tanner tool" International conference on Emerging trends in instrumentation,
communication, Electrical & Electronics Vaishnav Institute of Technology.
Shiraj Hussain, U.B.S. Chandrawat "A novel approach to reduce power dissipation of generic
logic circuits", International conference on Emerging trends in instrumentation,
communication, Electrical & Electronics, Vaishnav Institute of Technology.
Kumar Arvind, Vijay Sharma, U.B.S. chandrawat “ A Novel fine Trench MOSFET with high
voltage isolation from smart power system”, International journal of innovative research in
Electrical, Electronics, Instrumentation and Control Engineering, Vol.4, issue1, January 2016
ISSN (online) 2321-2004
Kumar Arvind, Vijay Sharma, U.B.S. chandrawat “ Estimation of FBSOA of 100V Super
Junction Trench Power MOSFET”, International Journal of Interdisciplinary Research (IJIR),
Vol.- 2, Issue-2, 2016, ISSN 2454-1362